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is31lt3 9 32 integrated silicon solution, inc. ? www.issi.com rev. a , 8 / 14 /2013 1 high pf universal led driver general description IS31LT3932 is a universal led driver, whi ch can operate in fly - back , buck - boost and buck convertor. for isolation fly - back, it can achieve high pf , high current accuracy , 5 % load and line regulation an d w ide voltage input voltage range , without loop c ompensation. for buck convertor, it also can achieve high pf , high current accuracy, high efficiency, good load and line regulation and wide voltage input voltage range, without loop compensation. with very few components. IS31LT3932 has special power line sense and output voltage sense circuits, operates in primary feedback mode without opto - coupler and achieve stable output current control without any loop compensation. IS31LT3932 has multiple protectio ns to improve the system reliability, including led open circuit, led short circuit, uvlo, ovp, current sense resistor short, the primary over current limit and over temperature protections. preliminary features ? universal isolation and non - isolation ? sing le stage pfc fly - back ? no loop compensation required ? no opto - coupler required ? 3 % led current accuracy ? 5 % line regulation and load regulation ? wide input voltage: 85 ~ 265vac ? low start - up current(15ua) ? valley turn - on mosfet to achieve high efficiency for b uck application ? few external components ? 1a sourcing current and 2a sinking current ? multiple protections ? sop - 8 package application ? led bulb ? led tube lamp ? led par typical operating circuit vin fuse bd c1 c2 c3 c4 c5 c6 r1 r2 r3 r4 r5 rcs r6 r7 r9 d2 d5 d4 d3 led1 ledn tr q1 u1 3932 gate cs gnd opt vcc vsine ct fb r8 d1 figure 1 typical isolated operatin g circuit
is31lt3 9 32 integrated silicon solution, inc. ? www.issi.com rev. a , 8 / 14 /2013 2 pin configurations package top view sop - 8 p in descriptions pin name function 1 vsine power line voltage detection 2 opt isolation and non - isolation option pin floating: fly - back and buck - boost resistor to ground: bu ck sinusoidal 3 ct time setting through the resistor between pin and ground isolation: operation cycle time setting ) ( ct 300 8 . 0 50 ? = k r v v k f fb non - isolation: mos turn - off delay time setting when fb detects zero voltage ext r tdelay = ? 6 10 15 4 gnd ground 5 fb fly - back and buck - boost : operation frequency is regulated through this pin to compensate output current non - isolation: valley turn - on detect pin, the external mos turns on after a short delay when fb detects zero voltage 6 cs inductor current sense 7 gate driver output to the external power mos 8 v cc power supply input pin, at a range of 7v~30v ordering information order part no. package qty/ r eel is31 lt39 32- gr ls2 - tr sop - 8 , lead - free 2500
is31lt3 9 32 integrated silicon solution, inc. ? www.issi.com rev. a , 8 / 14 /2013 3 absolute maximum ratings parameter value vdd,gate to g nd - 0.3 - 33.0 vsine, opt, ct, isen, fb to gnd - 0.3 - 6.0 operation temperature range(t a =t j ) - 40 - 125 junction temperature range - 40 - 150 storage temperature range - 65 - 150 esd h um a n bod y m ode 2000 vdd,gate to gnd - 0.3 - 33.0 stresses beyond thos e listed under ?absolute maximum ratings? may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these or any other condition beyond those indicated in the operational sections of the specification s is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability . electr ical characteristics (un less otherwise specified, v cc=1 6 v, fb=0v, vsine=2.5 v, r set = 300k : , and t amb =25 o c ) symbol parameter condition min typ e max unit v dd power supply range 8 30 v v ovp v dd over voltage threshold 34 v t ovp ovp reset time 160 ms ust startup voltage 15 16.5 18 v v uvlo under voltage lockout 7 v fb,ovp fb pin over voltage threshold 1.25 v t fb,ovp fb ov p reset time t cycle =20us 160 ms i in quiescent current vdd=16v w 700 1000 ua i in,st startup current vdd=10v 15 20 ua i op operation current 600 800 ua v csth peak current voltage threshold 495 500 505 mv v ocp over current voltage threshold 700 mv t ocp ocp reset time 40 ms t blank current sense blanking time v cs =v csth +50mv 600 ns t off_min minimum toff time opt=0 0.7 1 1.3 us t cycle operating cycle note1 v fb =0.8v, r ct =300k 19.8 20 20.2 us v fb =1.04v, r ct =300k 15.0 15.4 15.8 us v fb =0.56v, r ct =300k 28.2 28.6 29.0 us v gate ,max gate output clamp voltage vdd=20v 17.5 v isource sourcing current vgate=0v 0.22 a isink sinking current vgate=16v 0.57 a t p thermal shutdown threshold 150 o c t p thermal shutdown hysteresis 50 o c t re isen short protection reset time 40 ms
is31lt3 9 32 integrated silicon solution, inc. ? www.issi.com rev. a , 8 / 14 /2013 4 typical performance characteristics (vin=85~265vac,vout=14~30vdc,iout= 19 0ma) figure 4 pf figure 6 line regulation figure 8 efficiency vs vin(vac) figure 5 load regulation figure 7 thd vs leds
is31lt3 9 32 integrated silicon solution, inc. ? www.issi.com rev. a , 8 / 14 /2013 5 block d iagram figure 9 block diagram
is31lt3 9 32 integrated silicon solution, inc. ? www.issi.com rev. a , 8 / 14 /2013 6 application information ( base on figure 18 typical application circuit ) startup voltage when the vcc pin of the IS31LT3932 reaches 16.5v, the ic is allowed to start. after power is applied to the circuit, r 6 and r10 pr ovides a trickle current to allow c 9 to begin charging. the ic starts working when the voltage of c 9 reaches the start threshold for the ic. the value of r 6 and r10 & c 9 can be determined by the input voltage. larger values of r6 and r10 increase the st artup time, but reduce the losses after the circuit is ru nning. a low esr capacitor of 10 uf, 50v is recommended for c 9 . figure 1 0 startup soft start control when the device get start the threshold voltage of cs form low level go to 0.5v step by step. figure 1 1 soft start gate output voltage clamp IS31LT3932 has the voltage clamp for gate output. when the voltage of vcc small er than the v gate clp threshold , the voltage of gate output is about vcc. when the voltage of vcc is greater than v gateclp t hreshold , the voltage of gate is v gateclp threshold . figure 1 2 gate clamp vsine detection network and active pfc the voltage of vsine pin is used to control the waveform of input current make it follow the input voltage waveform, so can get the high p f and low thd. as figure 11: figure 1 3 active pfc the input pin, vsine is used to detect the input voltage which controls the peak current waveform in the inductor and in side agc makes the peak current of inductor constant , t his allows the is31l t3932 to actively correct the power factor and constant power during operation . the maximum input voltage of the vsine pin is 2.5v. this resistor network should be computed such that the peak input voltage condition corresponds to ~2.4vdc. thus, for 265 vac, the peak voltage is 374.7v. at 374.7v input, the output of the network shoul d be 2.4v, thus values of r 5+r9 = 2 m and r 18 = 1 3 k are appropriate. high tolerance vcc gate vcc gate vcc ip - pk v bulk ip - pk
is31lt3 9 32 integrated silicon solution, inc. ? www.issi.com rev. a , 8 / 14 /2013 7 resistors of 1% should be used. a small, 1nf capacitor, c 7 , is used to filter high freque ncy noise. working frequency the working frequency is set by connecting a resistor between the fset pin and ground. the relationship between the frequency and resistance is: ) ( 250 1 50 ? = k r v v k f ct fb output open circuit protection open circuit protection i s realized by connecting a resistor network to the fb pin. by sensing the voltage of the auxiliary winding, which is proportional to the output voltage, the IS31LT3932 detects when there is an open circuit condition on the secondary and stop the switching action. the threshold voltage for the fb pin is 1.25v. figure 1 4 ovp output short circuit protection if the output of the circuit is suddenly shorted, the voltage of the secondary winding is quickly reduced. this in - turn reduces the reflected voltag e in the auxiliary winding, so vcc of the device drops rapidly. if the vcc voltage drops below the uvlo, the device will stop switching, thus indirectly achieving output short circuit protection. figure 1 5 output short circuit protect uv lo protection the device will not operate if the vcc voltage is below the under - voltage lockout threshold. until the vcc voltage get startup threshold , t he device start again. cs over current and maximum duty cycle protection if the cs pin is shorted to ground, the device can no longer detect the peak current of the inductor, and thus will quickly cause damage to the power mos, inductor, or other circuit components. the maximum duty cycle of the gate is limited to 62.5 % internally to prevent a shorted cs pin from going into current runaway. when the duty cycle greater than 62.5% the gate will turn off 80ms. in addition to the duty cycle limit protection, there is also an inductor over current protection. if a fault condition exists wherein the inductor current continues to increase cycle per cycle, this would eventually cause the inductor into an over current condition. however, if the vcs pin rises to 0.7v, the nmos will immediately be shut off by the driving the gate low for a period of 40ms, after wh ich the device will attempt a restart. l oad regulation frequency control is controlled by the fb pin voltage, when the fb pin voltage in the range of 0.5~1.25v, the control voltage is proportional to the frequency and fb, when the fb voltage is less than 0.5v, the frequency remained unchanged. because the auxiliary winding voltage and the output voltage is the transformer turns ratio relationship, the fb pin detection auxiliary winding voltage, so, fb voltage follower output voltage changes, namely control frequency following the change of output voltage, in order to achieve constant output current. transformer design vcc gate vcc gate
is31lt3 9 32 integrated silicon solution, inc. ? www.issi.com rev. a , 8 / 14 /2013 8 the transformer technique is the other document of issi, here p lease use the ? 3932 calculator? to design the transformer. pcb design considerations (1) as figure 30 and 31 shows, c omponents such as c7,r1 7 ,r1 8 , r20,r21, r22,r23, c9 etc. w hich are connected to the ic should be mounted as close to the ic as possible. (2) bypass capacitors should always be mounted as close to the ic as possible. (3) s witc hing signal traces should be kept as short as possible and not be routed parallel to one another so as to prevent coupling. figure 1 6 typical pcb top layer out figure 1 7 typical pcb bottom layer out
is31lt3 9 32 integrated silicon solution, inc. ? www.issi.com rev. a , 8 / 14 /2013 9 typical application circuit ( it is suit ed to full input voltage 1 5 ~3 0 v - 0. 2 a output a p plications ) vin f1 bd1 mb6s c1 100nf c7 1nf c2 1nf 1kv c9 10uf c10 1uf c3 220uf 50v r5 1m r18 13k r17 240k r3 300k r20 1.0 r22 240k r23 10k r8 nc d2 fr107 d4 1n4148 d5 es1j d1 sb5200 led+ led- tr ee16 q1 2n60 u1 IS31LT3932 gate cs gnd opt vcc vsine ct fb r7 200 d6 1n4007 r2 5.1k l2 3.3mh l3 3.3mh r13 5.1k l1 3.3mh r9 1m r6 300k r10 300k r21 nc cy 1nf 1kv r1 nc c1 nc c4 220uf 50v c5 nc d7 39v figure 18 typical isolated a pplication schematic vin f 1 bd 1 mb 6 s c 1 100 nf c 7 1 nf c 2 1 nf 1 kv c 9 10 uf c 10 1 uf c3 220uf 50v r5 1m r18 13k r17 240k r3 150k r20 1.0 r22 240k r23 10k r8 nc d2 fr107 d4 1n4148 d5 es1j d1 sb5200 led- led+ tr ee16 q1 2n60 u1 IS31LT3932 gate cs gnd opt vcc vsine ct fb r7 200 d6 1n4007 r2 5.1k l2 3.3mh l3 3.3mh r13 5.1k l1 3.3mh r9 1m r6 300k r10 300k r21 nc r1 nc c1 nc c4 220uf 50v c5 nc d7 39v . figure 19 typical non- isolated a pplication schematic
is31lt3 9 32 integrated silicon solution, inc. ? www.issi.com rev. a , 8 / 14 /2013 10 cl assification reflow profile s profile feature pb - free assembly preheat & soak temperature min (tsmin) temperature max (tsmax) time (tsmin to tsmax) (ts) 150c 200c 60- 120 seconds average ramp - up rate (tsmax to tp) 3c/second max. liquidous temperature (tl) time at liquidous (tl) 217c 60- 150 seconds peak package body temperature (tp)* max 260c time (tp)** within 5c of the specified classification temperature (tc) max 30 seconds average ramp - down rate (tp to tsmax) 6c/second max. time 25c to peak temperature 8 minutes max. classification p rofile
is31lt3 9 32 integrated silicon solution, inc. ? www.issi.com rev. a , 8 / 14 /2013 11 tape and reel information
is31lt3 9 32 integrated silicon solution, inc. ? www.issi.com rev. a , 8 / 14 /2013 12 package information

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